Sentiment

Positive
at the heart of the chip design effort crafting and building the technology that fuels Apple's devices help deliver the next groundbreaking Apple products

Graphics Design Verification Engineer

Publisher: The Muse

Company: Apple

Location: Austin, TX

Date Posted: 01/22/2025

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Sentiment

Positive
competitive salary benefits and opportunities

Analog & Mixed Signal Verification Engineer

Publisher: The Muse

Company: Meta

Location: Redmond, WA

Date Posted: 01/22/2025

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Sentiment

Positive
verification methodology suitable for the IP develop detailed test and coverage plans ensuring bug-free first silicon

Design Verification Engineer

Publisher: The Muse

Company: Apple

Location: Austin, TX

Date Posted: 01/22/2025

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Sentiment

Positive
hands-on verification experience of bus fabric NOC AHB

Design Verification Engineer

Publisher: The Muse

Company: Apple

Location: Sunnyvale, CA

Date Posted: 01/23/2025

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Sentiment

Positive
+ 1 tags be or bc full time

Oral and Maxillofacial Surgeon

Publisher: healthecareers.com

Company: Vermont Oral Surgery

Location: Burlington/Stowe, VT

Date Posted: 01/23/2025

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Sentiment

Positive
experienced in successful tape-out of ASIC chips good at teamwork and able to help team development Lead project verification

Principal Design Engineer

Publisher: The Muse

Company: Cadence

Location: Nanjing, China

Date Posted: 01/22/2025

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Sentiment

Positive
contributing to Google's direct-to-consumer products planning verification of multimedia Intellectual Properties experience with System Verilog Assertions (SVA)

Senior Multimedia Design Verification Engineer, Silicon

Publisher: The Muse

Company: Google

Location: Taipei, Taiwan

Date Posted: 01/22/2025

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Sentiment

Positive
motivated proactive engineer expand Starlink's performance and capabilities

Sr. ASIC Design Verification Engineer (Silicon Engineering)

Publisher: The Muse

Company: SpaceX

Location: Irvine, CA

Date Posted: 01/22/2025

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Sentiment

Positive
collaborate with cross-functional teams 5+ years hands-on experience innovative ASIC solutions

ASIC Engineer, Design Verification

Publisher: The Muse

Company: Meta

Location: Bangalore, India

Date Posted: 01/23/2025

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Sentiment

Positive
Using SystemVerilog for constrained-random verification environments Managing projects monitoring vendors

ASIC Design Verification Engineer, Machine Learning, Early Career

Publisher: The Muse

Company: Google

Location: Madison, WI

Date Posted: 01/23/2025

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Sentiment

Positive
Good communication skills in English and a strong desire for working in a global environment Experience on UVM methodology or similar one should be preferred hands-on

Lead Customer Engagement Engineer - Xcelium

Publisher: The Muse

Company: Cadence

Location: Seoul, South Korea

Date Posted: 01/22/2025

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Sentiment

Positive
strong knowledge of SystemVerilog UVM and SystemVerilog Assertions

Senior Functional Verification Applications Engineer

Publisher: The Muse

Company: Siemens Digital Industries Software

Location: Remote

Date Posted: 01/22/2025

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